The invention relates to acquisition of data from a rotor.
There are many situations in which it is desirable to capture data from a moving body such as a turbine rotor. Heretofore, the approach has been to communicate data via slip rings and one approach to achieving this is described in PCT Patent Specification No. EP0798884. In this approach there is frequency modulation and multiplexing across an optical slip ring. Because there is frequency modulation data integrity is not affected by unexpected intensity variations and because of signal overlap between adjacent transmitters and continuity of the signal is ensured. However, for some environments such data transfer is not suitable because of electromagnetic noise, bandwidth restrictions, resolution and FDM tuning problems, and the physical size of the analog circuitry required. These difficulties apply particularly if rotor speeds arc quite high, in excess of 7000 rpm.
It is therefore an object of the invention to provide a data capture system to overcome these problems.
The present invention relates to a data capture system for interfacing with transducers and for transferring data to an external host system. The data capture system acquires data from a rotor. The data capture system is part of the rotor and includes analog to digital converters for converting analog data from transducers to digital data. The digital data is stored in a memory. The data capture system includes a host interface for communicating the data with an external host system. The capture system includes a data processor which receives the data from the analog to digital converters and writes the data to memory and controls the uploading of data from the memory to the external host system and for receiving control commands through the host interface.
The data capture system of the present invention includes a plurality of physically separate circuits mounted within a rotor which rotates symmetrically about the rotor axis.
analog to digital converters for converting transducer analog signals to digital data;
a memory;
a host interface for communication of data with an external host system; and
a data processor comprising means for receiving data from the analog to digital converters, for writing said data to the memory and for controlling upload of data from the memory to an external system and for receiving control commands via said host interface.
In one embodiment, the processor comprises means for operating in a cycle comprising a ready mode, a data capture mode, and return to a ready mode, and for initiating the cycle according to commands received from an external host.
In one embodiment, the processor comprises means for writing data to a mapped memory section during the ready modes and for repeatedly over-writing said memory section.
In another embodiment, the system further comprises a low pass filter and the processor comprises means for writing only a portion of the samples to the memory and for activating said filter during the ready modes.
In one embodiment, the processor comprises means for writing data to the memory in a sequential pattern according to time of receipt, and for directing upload of the data in said pattern.
In another embodiment, the processor comprises means for writing data words to the memory in sequence, each word comprising all simultaneous data from all analog to digital converters.
In one embodiment, the system further comprises:
a signal conditioning circuit comprising means far conditioning received transducer signals, and
an amplifier for the output of the signal conditioning circuit
In one embodiment, the system comprises a plurality of physically separate circuits, each comprising analog to digital converters, a processor, and a memory, each circuit being of elongate shape and comprising means for mounting within a rotor symmetrically about the rotor axis.
In a further embodiment, the system comprises a master clock source connected to all of the processors, and each processor comprises means for operating according to a high frequency clock for processor operations and according to a lower frequency dock for host interfacing operations.
In one embodiment, the host interface comprises a serial interface associated with each processor.
In one embodiment, each processor has an associated serial interfacing clock source and comprises means for synchronising the interfacing clock according to the master clock.
In another embodiment, each processor comprises means for operating according to state machines and the system comprises means for providing a synchronised state machine clock to all processors.
In a further embodiment, each processor comprises means for operating according to two state machines (M1, M2), one operating at a lower frequency than the other.
In one embodiment, the state machine operating at the lower frequency is used for putting the analog to digital converters into standby mode, for synchronising the analog to digital converters, and for initiating a calibration cycle for the analog to digital converters.
In another embodiment, each processor comprises means for also using the lower frequency state machine for transmitting status data to an external host via the host interface.
In a further embodiment, each processor comprises means for using the higher-frequency state machine to control read-back of stored data and for sending status data to a host.
Preferably, each processor comprises means for interlinking the state machines via a re-timing circuit.
In one embodiment, re-timing circuit comprises a D-type flip-flop.